Designers of ICs use electronic design automation (EDA) tools, a category of computer aided design (CAD) tools, to create a functional circuit design, including a register transfer level (RTL) representation of the functional circuit design, synthesize a “netlist” from the RTL representation, and implement a layout from the netlists. Synthesis of the netlist and implementation of the layout involve simulating the operation of the circuit and determining where cells should be placed and where interconnects that couple the cells together should be routed. EDA tools allow designers to construct a circuit, simulate its performance, estimate its power consumption and area and predict its yield using a computer and without requiring the costly and lengthy process of fabrication. EDA tools are indispensable for designing modern ICs, particularly very-large-scale integrated circuits (VSLICs). For this reason, EDA tools are in wide use.
Multiple EDA tools may be used when designing an IC. To manage the combination of the EDA tools that are used to design an IC, design flows are typically used. One type of design flow supports a hierarchical design methodology that allows designers to address problems on the physical side of the design process between logic synthesis and the implementation process. Through early analysis and floor planning, designers can apply physical constraints to assist in controlling the initial implementations of an IC design. Floor planning involves planning for the placement of components in an IC such as a Systems-on-Chip (SoC) where large hierarchical blocks are integrated. With a hierarchical design flow, EDA tools can allow a designer to reduce the number of iterations that occur post-RTL (assuming RTL is good) to create a realizable SoC. The iterations primarily occur to meet the design timing, power, area, etc.
Current hierarchical design flows may be derived from two dominant design methodologies, top-down and bottom-up. Typically, commercial methodologies are targeted at top-down design and in-house methodologies target bottom-up design gap that commercial methodologies do not accommodate. Design teams may also craft their own local methods for IC design. While these methods may be effective in local situations, local design methods may include assumptions that can prove to be ineffective in reaping the full benefits of a hierarchical design flow. This may be especially true when the hierarchical design flow is being used for parallel development over geographically distributed design teams. For example, in a geographically distributed organization, the true benefits of a hierarchical design flow can be achieved when designs are hierarchically split and geographically distributed for parallel execution. Communication problems between the various design teams, however, can lead to a final IC design that does not function properly or at least can delay achieving a workable final IC design.